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DTSTART:19700308T020000
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DTSTAMP:20260402T024533Z
LOCATION:3010\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T143000
DTEND;TZID=America/Los_Angeles:20250624T150000
UID:dac_DAC 2025_sess254_SSSN025@linklings.com
SUMMARY:Device-Aware Test: A Means to Attack Unmodeled Defects
DESCRIPTION:Said Hamdioui (Delft University of Technology)\n\nThis talk di
 scusses a new test approach called Device-Aware Test (DAT) and applies it 
 to industrial STT-MRAMs designs. DAT is a new test approach that goes beyo
 nd Cell-Aware Test; it does not assume that a defect in a device can be mo
 deled electrically as a linear resistor (as the state-of-the art approach 
 suggests), but it rather incorporates the impact of the physical defect in
 to the technology parameters of the device and thereafter in its electrica
 l parameters. Once the defective electrical model is defined, a systematic
  fault analysis is performed to derive appropriate fault models and subseq
 uently test solutions. DAT is demonstrated on real STT-MRAM chips, which s
 uffer from unique defects such as pinhole, synthetic anti-ferrimagnet flip
 , back-hoping, etc. The measurements show that DAT sensitizes realistic fa
 ults as well as new unique defects and faults that can never be caught wit
 h the traditional approaches.\n\nTopics: EDA\n\nSession Chair: Mehdi B. Ta
 hoori (Karlsruhe Institute of Technology, Faculty of Computer Science)\n\n
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