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DTSTAMP:20260402T024534Z
LOCATION:3010\, Level 3
DTSTART;TZID=America/Los_Angeles:20250623T163000
DTEND;TZID=America/Los_Angeles:20250623T170000
UID:dac_DAC 2025_sess257_SSSN041@linklings.com
SUMMARY:Multi-Scale Thermal-Mechanical Modeling of Advanced Chips
DESCRIPTION:Connor McClellan (DeepSim)\n\nAs silicon transistor scaling sl
 ows, advancements in packaging and 3DIC technologies have become essential
  for improving semiconductor system performance. However, these technologi
 es introduce significant thermal and mechanical design complexities, which
  can drastically reduce reliability and yields. To overcome thermal-stress
  challenges, multi-scale physics simulations are needed to identify design
  flaws before mass production. However, existing modeling tools struggle t
 o scale to complex systems. In this presentation, we showcase an AI-accele
 rated, multi-scale thermal-stress simulator that enables highly accurate s
 imulations with up to 1000x speedups over traditional finite element metho
 d solvers. This framework utilizes specialized AI models to simulate therm
 al stress across systems, from centimeter-scale interposers down to nanome
 ter-scale interconnects and vias, all within a single, comprehensive simul
 ation. With this approach, engineers can explore, identify, and resolve th
 ermal-stress design challenges early, ultimately shortening development cy
 cles and reducing time-to-market for advanced semiconductor chips.\n\nTopi
 cs: Design\n\nSession Chair: Sumeet Gupta (Purdue University)\n\n
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