BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260402T024533Z
LOCATION:3010\, Level 3
DTSTART;TZID=America/Los_Angeles:20250624T153000
DTEND;TZID=America/Los_Angeles:20250624T160000
UID:dac_DAC 2025_sess259_SSSN046@linklings.com
SUMMARY:Advanced Package Design & System Co-Optimization for Heterogeneous
  Integration
DESCRIPTION:Lalitha Immaneni (Intel Corporation)\n\nHeterogeneous integrat
 ion has moved from a novel concept just a few years ago to a mainstay in t
 he computer industry.  Advanced packaging is a key part of any chiplet arc
 hitecture strategy.  The concept of heterogeneous integration is inviting,
  with the ability to mix and match chiplets from different design sources 
 as well as foundry nodes.  This enables scaled architectures to address hi
 gh-computing needs for memory and enhanced compute with accelerators.  The
  approach also promises cost-optimization and faster time to market.  All 
 these benefits cannot be realized, however, without careful consideration 
 of the advanced packaging design and the optimization of the package desig
 n within the system construct.  This includes co-optimization all the way 
 from silicon to the system, and packaging is in the middle of this and cri
 tical.  This talk covers the key role that advanced packaging plays in ena
 bling optimized chiplet architectures and the important design considerati
 ons.  Key trade-off studies that are needed early in the concept phase wil
 l be discussed, highlighting areas like power, thermal, I/O, mechanical an
 d cost.  The talk will touch upon co-design, early architecture studies, s
 tandards, and the need for interoperable tools/flows/methods as well as in
 novations in design and optimization approaches to ensure optimum performa
 nce while keeping cost in mind.\n\nTopics: Design\n\nSession Chair: Yu Cao
  (University of Minnesota)\n\n
END:VEVENT
END:VCALENDAR