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BEGIN:VEVENT
DTSTAMP:20260402T024533Z
LOCATION:Level 3 Lobby
DTSTART;TZID=America/Los_Angeles:20250622T180000
DTEND;TZID=America/Los_Angeles:20250622T190000
UID:dac_DAC 2025_sess261_RESEARCH1117@linklings.com
SUMMARY:Speeding Up Global Placement Method by Integrating a Precorrected 
 FFT Solver
DESCRIPTION:Hangyu Zhang (University of Minnesota, Twin Cities) and Sachin
  S. Sapatnekar (University of Minnesota)\n\nGlobal placement is essential 
 for high-quality and efficient circuit placement, particularly in complex 
 modern VLSI designs. Recent advancements, such as electrostatics-based ana
 lytic placement, have improved scalability and solution quality. This work
  demonstrates that using the precorrected FFT technique for electric field
  computation significantly reduces runtime. Experimental results on standa
 rd benchmarks show a 2.73x speedup in FFT computation and a 29% total runt
 ime improvement against a conventional-FFT-based approach, and a 1.0% redu
 ction of scaled half-perimeter wirelength after detailed placement, paving
  the way for efficient global VLSI placement.\n\nTracks: DES5: Emerging De
 vice and Interconnect Technologies\n\n
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