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DTSTAMP:20250625T183019Z
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DTSTART;TZID=America/Los_Angeles:20250622T180000
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UID:dac_DAC 2025_sess261_RESEARCH1176@linklings.com
SUMMARY:MERINDA: Model Recovery in FPGA based Dynamic Architecture
DESCRIPTION:Bin Xu, Ayan Banerjee, and Sandeep Gupta (Arizona State Univer
 sity)\n\nRecovering underlying governing equations, i.e., model recovery (
 MR) from data - crucial for runtime monitoring - is one of the key solutio
 ns for assurance of safe and explainable operations of mission-critical au
 tonomous systems (MCAS). MCAS often operate under strict constraints relat
 ed to time, computational resources, and power, potentially requiring the 
 usage of edge artificial intelligence (edge-AI) for accelerated safety mon
 itoring. Field Programmable Gate Arrays (FPGAs) have emerged as an ideal s
 olution to meet these constraints due to their reconfigurability and capac
 ity for hardware-optimized performance. MR approaches such as EMILY or Phy
 sics informed neural networks with sparse regression (PINN+SR), use contin
 uous depth residual networks and continuous time latent variable models e.
 g. Neural ODE (NODE) as core components. A key challenge in accelerating t
 hese components comes from the iterative approach towards integration of o
 rdinary differential equations (ODE) in the forward pass. This paper intro
 duces a novel FPGA-based accelerated model recovery in dynamic architectur
 e (MERINDA) approach, that utilizes equivalent neural architectures to the
  NODE core that are amenable for acceleration. MERINDA has four components
 : a) a Gated Recurrent Unit (GRU) layer that generates approximate discret
 ized solution of the original NODE layer in EMILY or PINN-SR, b) a dense l
 ayer to solve the inverse ODE problem to obtain approximate ODE model coef
 ficients from the discretized solutions, c) sparsity driven dropout layer 
 to reduce model order, and d) a standard ODE solver to solve the reduced o
 rder ODE and regenerate the continuous time original output of the NODE la
 yer. Components a and b can be accelerated using FPGA, while c and d  have
  much less computational complexity than the original NODE layer. We first
  theoretically prove that the MERINDA is equivalent to EMILY and empirical
 ly compare their MR performance on four benchmark examples. We then assess
  the accuracy, processing speed, energy consumption, and DRAM access of ME
 RINDA and compare with baseline accelerated machine learning approaches su
 ch as non-physics informed machine learning (ML), and learning with only p
 hysics guided loss functions (ML-PG). We also compare MERINDA with  GPU-ba
 sed implementations of all three approaches to evaluate the advantage of a
 cceleration. Finally, we apply mixed integer programming to identify the o
 ptimal approach towards runtime monitoring and its hyper-parameters under 
 various resource constraints. Our results demonstrate substantial improvem
 ents in energy efficiency, training time, and DRAM access with minimal com
 promises in accuracy, underscoring the viability of MERINDA for resource-c
 onstrained autonomous systems.\n\n
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