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DTSTAMP:20260402T024533Z
LOCATION:Level 3 Lobby
DTSTART;TZID=America/Los_Angeles:20250622T180000
DTEND;TZID=America/Los_Angeles:20250622T190000
UID:dac_DAC 2025_sess261_RESEARCH1347@linklings.com
SUMMARY:TickTockStack: In-Datapath Current Imbalance Elimination Using Clo
 cked Differential Logic in a Voltage Stacked Vector Processor
DESCRIPTION:Michał Gorywoda and Wanyeong Jung (Korea Advanced Institute of
  Science and Technology (KAIST))\n\nIn modern chips, much of the power is 
 wasted on the power delivery network, causing thermal issues and voltage d
 rops, which reduces the system's reliability. The voltage stacking techniq
 ue addresses this problem by reusing charge in similar activity circuits. 
 Still, it suffers from stack voltage ripple and power delivery loss due to
  the current imbalance caused by the activity factor variation in CMOS log
 ic. This work presents a balancing technique that uses clocked differentia
 l logic with constant activity factor to eliminate current imbalance on a 
 gate level in an entire SIMD processor datapath. Applied to a voltage\nsta
 cked vector processor called TickTockStack, it achieves a 7.6x reduction o
 f stack voltage ripple and a 33.5% smaller power delivery loss compared to
  the CMOS baseline with an 18.4% area overhead and without a significant i
 mpact on the performance.\n\nTracks: DES5: Emerging Device and Interconnec
 t Technologies\n\n
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