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UID:dac_DAC 2025_sess261_RESEARCH1642@linklings.com
SUMMARY:Sayram: A Hardware-software Co-design to Accelerate Wireless Baseb
 and Processing
DESCRIPTION:Xinbing Zhou (Hainan University), Shaobo Shi and Shaohan Liu (
 Ultichip Communication Technology), Peng Hao (Northwestern Polytechnical U
 niversity), Yunxiang Tang (Ultichip Communication Technology), Yi Man (Bei
 jing University of Posts and Telecommunications), and Dake Liu (Ultichip C
 ommunication Technology)\n\nMicro base stations, with limited antennas and
  extensive deployment, require scaled-down hardware. Traditional Software 
 Defined Radio (SDR) solutions (e.g., CPU, manycore systems, GPU) offer fle
 xibility but incur high area and power costs, while DSP lacks efficient ac
 celeration for smaller configurations. The key challenge is achieving mini
 mal area and power overhead while meeting 5G requirements. This paper pres
 ents a hardware-software co-designed architecture, Sayram, which minimizes
  overhead for 5G physical layer processing. Sayram integrates an instructi
 on fusion mechanism, along with the compiler for simplified programming, a
 nd a Vector Indirect Addressing Memory (VIAM) to minimize memory access cy
 cles, boosting overall processor efficiency. Operating at 1 GHz, Sayram ac
 hieves 158 Gops with a 1.18 mm² area, supporting 2T2R and 4T4R PUSCH proce
 ssing in single-core and dual-core modes, respectively.  Evaluations show 
 that Sayram's area efficiency is 48×, 180×, and 2591× higher than manycore
 , DSP, and CPU architectures, with power efficiency improvements of 54×, 3
 62×, and 4400×, respectively.\n\nTracks: DES5: Emerging Device and Interco
 nnect Technologies\n\n
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