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DTSTAMP:20260402T024533Z
LOCATION:Level 3 Lobby
DTSTART;TZID=America/Los_Angeles:20250622T180000
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UID:dac_DAC 2025_sess261_RESEARCH171@linklings.com
SUMMARY:SCMG: Scalable and Configurable FPGA-based Multiplier Generator us
 ing Integer Linear Programming
DESCRIPTION:Yao Shangshang (Independent Researcher) and Zhu Junyi, Lang Qi
 ngjie, Wang Ruoxi, and Shen Li (National University of Defense Technology)
 \n\nHigh-performance multipliers are critical components across numerous a
 pplications. While FPGAs utilize DSP blocks for efficient multiplication, 
 their limited quantity, fixed placement, and potential for timing closure 
 issues necessitate the exploration of alternative solutions. Logic-based s
 oftcore multipliers offer a promising solution, but existing FPGA-oriented
  implementations predominantly focus on heuristic small-scale multipliers,
  lacking the scalability and holistic optimization required for larger ins
 tances. Moreover, prior designs neglect the tunable balance between latenc
 y and resource utilization, employing fixed logic depth and cost, thereby 
 limiting their adaptability to different scenarios. This paper introduces 
 SCMG, a Scalable and Configurable FPGA-based Multiplier Generator that emp
 loys Integer Linear Programming (ILP) to overcome these limitations. SCMG 
 offers flexible configuration of multiplier size and logic levels, enablin
 g application-specific performance-prioritized or cost-prioritized optimiz
 ation. The ILP-based approach efficiently generates optimal designs tailor
 ed to specific resource constraints and performance targets. Furthermore, 
 SCMG supports the efficient generation for approximations, providing a val
 uable option for fault-tolerant applications. Experimental results demonst
 rate SCMG's significant advantages over AMD Vivado's built-in multiplier I
 P, achieving up to 23.3% area reduction, 15.6% latency improvement, and 24
 .5% energy efficiency enhancement. The tool is open-sourced to promote fur
 ther research and development in this area.\n\nTracks: DES5: Emerging Devi
 ce and Interconnect Technologies\n\n
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