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DTSTAMP:20260402T024532Z
LOCATION:Level 3 Lobby
DTSTART;TZID=America/Los_Angeles:20250622T180000
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UID:dac_DAC 2025_sess261_RESEARCH2131@linklings.com
SUMMARY:Schemato - An LLM for Netlist-to-Schematic Conversion
DESCRIPTION:Ryoga Matsuo and Stefan Uhlich (Sony Europe B.V., ZNL Deutschl
 and); Arun Venkitaraman, Andrea Bonetti, Chia-Yu Hsieh, and Ali Momeni (So
 nyAI); Lukas Mauch and Augusto Capone (Sony Europe B.V., ZNL Deutschland);
  Eisaku Ohbuchi (Sony Semiconductor Solutions); and Lorenzo Servadei (Sony
 AI)\n\nMachine learning models are advancing circuit design, particularly 
 in analog circuits. They typically generate netlists that lack human inter
 pretability. This is a problem as human designers heavily rely on the inte
 rpretability of circuit diagrams or schematics to intuitively understand, 
 troubleshoot, and develop designs. Hence, to integrate domain knowledge ef
 fectively, it is crucial to translate ML-generated netlists into interpret
 able schematics quickly and accurately. We propose Schemato, a large langu
 age model (LLM) for netlist-to-schematic conversion. In particular, we con
 sider our approach in the two settings of converting netlists to .asc file
 s for LTSpice and LaTeX files for CircuiTikz schematics. Experiments on ou
 r circuit dataset show that Schemato achieves up to 93% compilation succes
 s rate for the netlist-to-LaTeX conversion task, surpassing the 26% rate s
 cored by the state-of-the-art LLMs. Furthermore, our experiments show that
  Schemato generates schematics with a mean structural similarity index mea
 sure that is 3x higher than the best performing LLMs, therefore closer to 
 the reference human design.\n\nTracks: DES5: Emerging Device and Interconn
 ect Technologies\n\n
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