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DTSTAMP:20260402T024534Z
LOCATION:Level 3 Lobby
DTSTART;TZID=America/Los_Angeles:20250622T180000
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UID:dac_DAC 2025_sess261_RESEARCH2226@linklings.com
SUMMARY:Daedalus: a Floorplanning Strategy for Next-Generation 3D Chiplet 
 Integration
DESCRIPTION:Sebastiano Gaiardelli and Michele Lora (University of Verona);
  Marco Cignarella, Anna Fontanelli, Francesco Rossi, and Michele Taliercio
  (Monozukuri S.p.A); and Franco Fummi (University of Verona)\n\nThe design
  of three-dimensional integrated circuits (3D-ICs) is at the forefront for
  cost-effective and high-performance computing systems. 3D systems enable 
 the vertical stacking of multiple chiplets, reducing areas and interconnec
 tion lengths. On the other hand, the floorplanning of such systems require
 s more computational resources. To address this problem, we propose Daedal
 us, a framework supporting the design of 3D-ICs. Daedalus provides an envi
 ronment where multiple design constraints can be enforced, enabling to fin
 d the optimal configuration by exploring the solution space. The experimen
 tal results show the effectiveness of our method in solving floorplanning 
 with increasing complexity in a timely manner.\n\nTracks: DES5: Emerging D
 evice and Interconnect Technologies\n\n
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