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BEGIN:VEVENT
DTSTAMP:20260402T024534Z
LOCATION:Level 3 Lobby
DTSTART;TZID=America/Los_Angeles:20250622T180000
DTEND;TZID=America/Los_Angeles:20250622T190000
UID:dac_DAC 2025_sess261_RESEARCH2475@linklings.com
SUMMARY:Dynamic FPGA Acceleration for Cloud Workloads: A HLS-based JIT  Co
 mpilation Approach
DESCRIPTION:Rui Li and Shuang Cao (Dawn Computing)\n\nHigh-Level Synthesis
  (HLS) has transformed FPGA\nprogramming by allowing developers to describ
 e hardware\nfunctionality using high-level languages like C/C++. However,\
 nthe long synthesis time of traditional HLS tools hinder the\nflexibility 
 required to adapt hardware generation in real-time,\nparticularly in dynam
 ic environments such as the cloud. In this\npaper, we propose Nimble, a no
 vel Just-in-Time (JIT) compilation\nframework that brings runtime adaptabi
 lity to HLS, enabling\ntransparent FPGA acceleration on cloud workloads wi
 thout\nrequiring any hardware expertise. Our evaluation on real-world\napp
 lications demonstrated substantial performance gains with\nspeedups of up 
 to 3.2X in SQL query processing for MySQL.\n\nTracks: DES5: Emerging Devic
 e and Interconnect Technologies\n\n
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