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UID:dac_DAC 2025_sess261_RESEARCH2482@linklings.com
SUMMARY:MOOPSE: Leveraging High-Radix Booth Encoders for Area-Efficient Ma
 trix Multiply Operations
DESCRIPTION:Chenlin Shi (University of Electro-Communications); Toru Koizu
 mi (Nagoya Institute of Technology); Ryota Shioya (The University of Tokyo
 ); and Hayato Yamaki, Hiroki Honda, and Shinobu Miwa (University of Electr
 o-Communications)\n\nIn this paper, we propose MOOPSE (Matrix multiply Ope
 ration Optimization with Partially-Shared high-radix booth Encoder), a nov
 el matrix multiply unit (MMU) used in processor cores. A key feature of MO
 OPSE is the use of high-radix Booth encoders, which reduces the area of fu
 sed multiply add (FMA) units, improving the area-efficiency of MMUs. Altho
 ugh high-radix Booth encoders are rarely used in conventional FMA units du
 e to performance, power, and area overheads, our MOOPSE solves this issue 
 by sharing main internal components of Booth encoders between multiple FMA
  units. Our experimental results show that MOOPSE shows respective improve
 ments of up to 9%, 21%, 19%, and 16% in performance per area, dynamic powe
 r efficiency, leakage power efficiency, and area overhead compared to the 
 state-of-the-art MMU.\n\nTracks: DES5: Emerging Device and Interconnect Te
 chnologies\n\n
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