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DTSTAMP:20260402T024533Z
LOCATION:Level 3 Lobby
DTSTART;TZID=America/Los_Angeles:20250622T180000
DTEND;TZID=America/Los_Angeles:20250622T190000
UID:dac_DAC 2025_sess261_RESEARCH2582@linklings.com
SUMMARY:Multiple Row Buffer DRAM
DESCRIPTION:K. Chitra, Arjun Dey, and Aryabartta Sahu (Indian Institute of
  Technology, Guwahati) and Minesh Patel (Rutgers University)\n\nDRAM chips
  contain multiple banks to handle several memory requests in parallel. Whe
 n two memory requests try to access different rows of the same bank, it re
 sults in row buffer conflicts. Our objective in this work is to reduce row
  buffer conflicts by introducing multiple row buffers in each bank. We pro
 pose multiple row buffer DRAM, which employs a primary global row buffer a
 long with multiple secondary SRAM row buffers in the DRAM chip. These SRBs
  act as a cache, exploiting the spatial and temporal locality of memory re
 quests to enhance performance. Our evaluation shows that MRB-DRAM achieves
  an average improvement in Instructions per Cycle (IPC) of 27% for singlec
 ore systems and a weighted speedup increase of 24% for multicore systems i
 n DDR4 memory configurations with a modest area overhead of approximately 
 2%.\n\nTracks: DES5: Emerging Device and Interconnect Technologies\n\n
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