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DTSTART;TZID=America/Los_Angeles:20250623T180000
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UID:dac_DAC 2025_sess262_RESEARCH1075@linklings.com
SUMMARY:Modeling PFAS in Semiconductor Manufacturing to Quantify Trade-off
 s in Energy Efficiency and Environmental Impact of Computing Systems
DESCRIPTION:Mariam Elgamal (Harvard University); Abdulrahman Mahmoud (Moha
 med bin Zayed University of Artificial Intelligence); and Gu-Yeon Wei, Dav
 id Brooks, and Gage Hills (Harvard University)\n\nThe electronics and semi
 conductor industry is a prominent consumer of per- and poly-fluoroalkyl su
 bstances (PFAS), also known as forever chemicals. PFAS are persistent in t
 he environment and can bioaccumulate to ecological and human toxic levels.
  Computer designers have an opportunity to reduce the use of PFAS in semic
 onductors and electronics manufacturing, including integrated circuits (IC
 ), batteries, displays, etc., which currently account for a staggering 10%
  of the total PFAS fluoropolymers usage in Europe alone. In this paper, we
  present a framework where we (1) quantify the environmental impact of PFA
 S in computing systems manufacturing with granular consideration of the me
 tal layer stack and patterning complexities in IC manufacturing at the des
 ign phase, (2) identify contending trends between embodied carbon (carbon 
 footprint due to hardware manufacturing) versus PFAS. For example, manufac
 turing an IC at a 7 nm technology node using EUV lithography uses 18% less
  PFAS-containing layers, compared to manufacturing the same IC at a 7 nm t
 echnology node using DUV immersion lithography (instead of EUV) unlike emb
 odied carbon trends, and (3) conduct case studies to illustrate how to opt
 imize and trade-off designs with lower PFAS, while meeting power-performan
 ce-area constraints. We show that optimizing designs to use less back-end-
 of-line (BEOL) metal stack layers can save 1.7× PFAS-containing layers in 
 systolic arrays.\n\nTracks: DES5: Emerging Device and Interconnect Technol
 ogies\n\n
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