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DTSTAMP:20260402T024534Z
LOCATION:Level 2 Lobby
DTSTART;TZID=America/Los_Angeles:20250623T180000
DTEND;TZID=America/Los_Angeles:20250623T190000
UID:dac_DAC 2025_sess262_RESEARCH1119@linklings.com
SUMMARY:Analytical Optimization for Robust and Efficient Analog IC Design 
 Automation
DESCRIPTION:Alec Adair and Armin Tajalli (University of Utah)\n\nThis arti
 cle presents a methodology to automatically and optimally design and size 
 analog circuits through an analytically derived objective function and con
 straints based on given specifications, implement their layout, and produc
 e the corresponding Graphic Data System (GDS) files. To implement this flo
 w, a python implementation of the C/ID methodology is used for technology 
 characterization and lookup tables (LUTs) generation. An open source layou
 t generation platform is used for producing circuit layout from an optimiz
 ed design in an automatized flow. To adequately implement the flow, a meth
 od to analyze complexity of circuit networks, and the concept of ``reducib
 ility of problem dimension" is provided. An analytical approach is propose
 d to formulate a general and technology-agnostic optimization process that
  is expandable to high degrees of dimensionality for a wide variety of var
 ious circuit topologies, accounting for process and temperature variations
  while maintaining low computational complexity and high accuracy with no 
 simulation iterations required. The methodology and approach affords the a
 bility for clear visualization of design space and and optimums. From this
  analysis, technology-agnostic topology factors, compute complexity degree
 , and design scripts will be derived. A case study on a Current Mirror Ope
 rational Transconductance Amplifier (CM OTA) illustrates the approach, sho
 wing optimal design points for power minimization. The process includes SP
 ICE simulation, layout generation via the ALIGN analog layout generator, a
 nd an example using open source Electronic Design Automation (EDA) tools a
 nd Skywater's 130~nm  design kit, with results compared across analysis, s
 chematic, and post layout netlist simulations. All results, designs, and s
 cripts are publicly available for transparency and easy reproducability.\n
 \nTracks: DES5: Emerging Device and Interconnect Technologies\n\n
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