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DTSTAMP:20260402T024534Z
LOCATION:Level 2 Lobby
DTSTART;TZID=America/Los_Angeles:20250623T180000
DTEND;TZID=America/Los_Angeles:20250623T190000
UID:dac_DAC 2025_sess262_RESEARCH1452@linklings.com
SUMMARY:Synthesis of a memristor-transistor single-phase cell library and 
 its use to synthesize logic circuits
DESCRIPTION:Baishakhi Rani Biswas and Sandeep Gupta (University of Souther
 n California)\n\nMemristor, a passive fundamental circuit component, is a 
 promising candidate for implementing logic circuits. Memristors have extre
 mely low areas and are compatible with MOS devices. Recently, exhaustive e
 numeration was used to identify extremely low-area memristor-transistor lo
 gic cells. In this research, we propose the first constructive method for 
 synthesizing such cells with arbitrary numbers of inputs and devices. We a
 lso propose methods for cascading these cells to further improve area effi
 ciency and to carry out device-cell co-optimization to improve performance
 . We use these methods to create a comprehensive library of memristor-tran
 sistor logic cells and use this library to synthesize benchmark circuits u
 sing ABC. Logic synthesis results show that our cells dramatically reduce 
 the area for large logic blocks --- around 53% over CMOS cells and 25%  ov
 er MRL (a logic style that uses memristor-only cell+CMOS inverters) and pr
 ovide moderate power consumption.\n\nTracks: DES5: Emerging Device and Int
 erconnect Technologies\n\n
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