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DTSTAMP:20260402T024534Z
LOCATION:Level 2 Lobby
DTSTART;TZID=America/Los_Angeles:20250623T180000
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UID:dac_DAC 2025_sess262_RESEARCH2210@linklings.com
SUMMARY:Boolean Reasoning Guided Ungrouping
DESCRIPTION:Eleonora Testa, Giulia Meuli, Elena Teica, Alan Vaz, Vishal Ar
 alikatti, Abhishek Kumar, Brian Lockyear, and Luca Amaru (Synopsys)\n\nUng
 rouping is a key step in design implementation. This step is tasked to dis
 solve selected hierarchical boundaries in order to unlock more optimizatio
 n opportunities and logic sharing. \nDetermining the right amount of ungro
 uping is an important and challenging problem which requires new and innov
 ative technologies in logic synthesis. \nOn the one hand, ungrouping too m
 uch may impact the verifiability of the implemented netlist, reduce the sc
 alability of synthesis, and degrade the Quality of Results (QoR). \nOn the
  other hand, not ungrouping enough may fail to catch many optimization opp
 ortunities and degrade QoR even further. \nExisting solutions are mainly g
 uided by comparing the size of the children and parent hierarchies to be u
 ngrouped.\nIn this paper, we propose a novel ungrouping flow based on Bool
 ean reasoning. \nWe guide ungrouping with formal reasoning engines, such a
 s Boolean SATisfiability (SAT), considering logic sharing, connectivity, a
 nd Boolean optimization opportunities identified across the design. \nWe s
 how how this flow unlocks more QoR, keeps verification complexity containe
 d, and preserves the most advantageous hierarchical boundaries for synthes
 is. \nWe integrate our novel ungrouping flow within an industrial synthesi
 s tool, showing significant QoR improvement over the state-of-the-art solu
 tions.\n\nTracks: DES5: Emerging Device and Interconnect Technologies\n\n
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