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DTSTAMP:20260402T024534Z
LOCATION:Level 2 Lobby
DTSTART;TZID=America/Los_Angeles:20250623T180000
DTEND;TZID=America/Los_Angeles:20250623T190000
UID:dac_DAC 2025_sess262_RESEARCH2392@linklings.com
SUMMARY:DiReC: Enhancing VHDL Code Generation and Summarization with Divid
 e-Retrieve-Conquer Strategy
DESCRIPTION:Prashanth Vijayaraghavan (IBM Research); Apoorva Nitsure (IBM)
 ; Luyao Shi, Charles Mackin, Tyler Baldwin, and David Beymer (IBM Research
 ); and Ehsan Degan and Vandana Mukherjee (IBM)\n\nHardware description lan
 guages (HDLs), like VHDL, pose challenges for large language models (LLMs)
  due to limited data, syntactic complexity, and mismatched vocabularies. T
 o address these, we introduce the VHDL-IR dataset with diverse parallel da
 ta pairs and develop a custom retriever to align VHDL syntax, functionalit
 y, and natural language. Our Divide-Retrieve-Conquer (DiReC) strategy enha
 nces LLM performance by modularizing tasks, retrieving relevant contexts, 
 and integrating results for accurate outputs. Experiments show up to 20% i
 mprovement in code generation and 12% in summarization over standard RAG, 
 demonstrating DiReC's effectiveness while identifying areas for further VH
 DL-focused research.\n\nTracks: DES5: Emerging Device and Interconnect Tec
 hnologies\n\n
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