BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260402T024533Z
LOCATION:Engineering Posters\, Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250623T170000
DTEND;TZID=America/Los_Angeles:20250623T180000
UID:dac_DAC 2025_sess263_ENGPOST017@linklings.com
SUMMARY:A new methodology to generate a multitude of SoC configurations qu
 ickly
DESCRIPTION:Fernand Da Fonseca (Arm Ltd.) and Chouki Aktouf, Valentin Boye
 r, and Mael Rabe (Defacto Technologies)\n\nWithin Arm a new unit has been 
 built to provide SoC solutions to their customers. One of the biggest prob
 lems we faced when designing SoCs was need to rearrange the hierarchy to m
 atch physical implementation needs. As the targeted applications are highl
 y complex, changing the hierarchy manually or using traditional methodolog
 ies was not affordable.\nWe have developed a new flow based on Defacto's S
 oC Compiler to be able to generate multiple configurations within one day.
  The presented flow enables to generate a new SoC hierarchy of one of extr
 emely large Arm-based SoC design in just one hour rather than more than 24
 hours with the original way.\nThis flow enables to drastically reduce the 
 overall TAT to generate new RTL which leads to have much more RTL configur
 ations to explore and compare towards better PPA.\n\n
END:VEVENT
END:VCALENDAR
