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DTSTAMP:20260402T024534Z
LOCATION:Engineering Posters\, Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250623T170000
DTEND;TZID=America/Los_Angeles:20250623T180000
UID:dac_DAC 2025_sess263_ENGPOST233@linklings.com
SUMMARY:Real-time Process Margin-based Layout Optimization
DESCRIPTION:Collin Tranter, Navneet Jain, Romain Feuillette, David Pritcha
 rd, Heather Lazar, Nolan Pavek, Stephen Burgess, and Benoit Ramadout (Glob
 alFoundries)\n\nCreation of new special constructs, exploratory layouts, a
 nd design optimization is highly time and resource consuming. There is no 
 layout design method which makes all relevant design information readily a
 vailable. A layout design method which utilizes design information, design
  rule values, with the option to consider Si validated margin and AI predi
 cted margin information and PEX/parasitics information. Design information
  will be available to the user in a layout overlay, updating in real-time 
 with design/shape modifications, allowing for design optimization and crea
 tion of new special constructs. Margin information is obtained through Si 
 validation experiments, as well as default (non-experimental) values deter
 mined by process assumption and DR calculations. PEX information is obtain
 ed from existing PEX tables and interpolated values. Exploratory design an
 d margin prediction may reveal blind spots in design rule interactions, le
 ading to PDK improvement. Also discussed is the methodology to predict des
 ign rule margin compaction opportunities, using machine learning applied t
 o the Silicon validation data dataset.\n\n
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