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DTSTAMP:20260402T024532Z
LOCATION:Engineering Posters\, Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250623T170000
DTEND;TZID=America/Los_Angeles:20250623T180000
UID:dac_DAC 2025_sess263_ENGPOST267@linklings.com
SUMMARY:HBM Timing Methodology with Liberty LVF
DESCRIPTION:Eric Hsu and Ying Luo (Nvidia) and AN-JUI SHEY (Empyrean Techn
 ology)\n\nTiming OCV margin for mixed-signal IP blocks has been a single d
 erate value during timing closure and signoff.  This derate value must cov
 er all critical paths, resulting in significant over-margin for the vast m
 ajority of the timing paths with much smaller OCV requirements, which in t
 urn results in longer timing closure cycle and increased area and power.  
 Liberty LVF has been widely adopted in standard cell design, but it has no
 t crossed over into the modeling of large mixed-signal IP blocks due to th
 e prohibitive Monte Carlo runtime of these large and complex simulations. 
  We have collaborated with Empyrean to deploy their critical path based LV
 F characterization tool to generate LVF models for selected library arcs t
 hat are automatically merged into our in-house nominal Liberty files.  Thi
 s new characterization and timing methodology has been proven on the HBM d
 esign, and it resulted in expected and significant reduction in timing OCV
  margin.  Success from this new methodology is being proliferated to other
  mixed-signal design IPs.\n\n
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