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DTSTAMP:20260402T024533Z
LOCATION:Engineering Posters\, Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250623T170000
DTEND;TZID=America/Los_Angeles:20250623T180000
UID:dac_DAC 2025_sess263_ENGPOST294@linklings.com
SUMMARY:A Novel Test Point Insertion Methodology for Enhanced Test Efficie
 ncy and Improved Design Quality
DESCRIPTION:Pervez Garg and Piyushkumar Chaniyara (Texas Instruments)\n\nD
 evice test cost and DPPM are of paramount importance to gain market share 
 by offering quality devices at optimal price point. ATPG is the proven eff
 icient structural technique for testing and diagnosing silicon failures. I
 n large gate count devices (5M+ design flip-flops), meeting scan coverage 
 at entitlement has been challenging, resulting in higher scan pattern coun
 t and increased test time. Random resistant fault analysis (RRFA) based te
 st point insertion (TPI) can improve scan coverage with lower scan pattern
  count - a known methodology to improve device quality. However, because o
 f sheer design size, even 2% of design flops as test-points (TPs) leads to
  100k+ more flip-flops added in design, which is huge DFT area overhead. T
 his paper focuses on novel physical and timing aware TPI methodology, stra
 tegically re-purposing pre-existing functional/DFT flops in design as TPs.
  Further we propose observe-only TPs to gain scan coverage in DFT infrastr
 ucture blocks. This study evaluates the methodology across range of sub-ch
 ips, utilizing benefits of TPI and demonstrating substantial improvements 
 in test quality and test time while overcoming the shortcomings and concer
 ns of area overhead, routing congestion and power with TPs.\n\n
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