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DTSTAMP:20260402T024533Z
LOCATION:Engineering Posters\, Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250623T170000
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UID:dac_DAC 2025_sess263_ENGPOST327@linklings.com
SUMMARY:A constructive approach to Left-shift preliminary identification o
 f critical silicon breaking anomalies
DESCRIPTION:Ayushi Bapna and Arif Mohammed (Texas Instruments)\n\nWith myr
 iad complex SOCs, challenges in verification have increased manifold. One 
 of the challenging aspects of any SOC/IP verification is to identify the u
 n-initialized flops in a design and analyze them across all corner case sc
 enarios which, if not taken care, can lead to catastrophic silicon issues.
  Most of these when caught on silicon leads to re-spin of the device.\nHen
 ce it becomes extremely important to identify such cases in the design, ei
 ther in RTL phase or gate-level simulations and analyze their impact on th
 e design with due-diligence. There have been multiple cases where potentia
 l issues got masked due to random deposits in gate-level simulations, henc
 e escaping to silicon.\nWith SOC integration levels approaching a billion 
 transistors per chip, tremendous pressure to shrink the verification cycle
 , and power minimization, it becomes important to identify and resolve suc
 h potential bugs due to un-initialized/non-resettable flops in RTL verific
 ation stage (early enough in design cycle).\nFollowing paper proposes a co
 mplete & practical methodology along with case studies over various SOC si
 licon findings for early identification and left shift of potential silico
 n bugs that could easily escape due to un-initialized flops in any SOC. \n
 Here we leverage different tool support from Cadence and come up with a me
 thodology to which helps to identify potential bugs.\nWith case-studies do
 ne on various Silicon bugs, this novel methodology has proved to effective
 ly catch those un-initialized flops at RTL design stage itself.\n\n
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