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DTSTAMP:20260402T024533Z
LOCATION:Engineering Posters\, Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250623T170000
DTEND;TZID=America/Los_Angeles:20250623T180000
UID:dac_DAC 2025_sess263_ENGPOST328@linklings.com
SUMMARY:An Efficient Methodology of Analyzing Rush Current in Power Gated 
 Design
DESCRIPTION:Abhinav Gaur and Akhilesh Mishra (NXP Semiconductors) and Anku
 r Chavhan (Cadence Design Systems, Inc.)\n\n* Lumped model-based estimatio
 n can be done which is  faster, but it has accuracy issues. \n  Another wa
 y is we can do ramp-up analysis on complete design which is having multi-m
 illion node   \n which is more accurate. In this case simulation will run 
 from days to  weeks time as it measure \n voltage for each node.\n\n* Runn
 ing simulation for number of weeks to completely turn-on power net, may re
 sult in huge \n   impact on paid LSF services. Therefore, some voltage thr
 eshold-based solution is required\n\n* In early phase of a design, power g
 ates optimization plays an important and time-consuming role\n   Focus wou
 ld be to identify accurate number of power gates within a time frame\n    
 * How much time voltage waveform is taking to reach 80/90 % of ideal volta
 ge \n    * Can we do adaptive resolutions-based runs, or can we cut down t
 he simulation when switched \n       nets are above used defined threshold
 .\n\n * In  early stage of design implementation cycle, Design Scenarios l
 ike Isolated islands, power gates \n   triggering issues, irregular turn-o
 n time of power gates etc. came in picture.\n\n * otherwise doing early ra
 mp-up analysis, debugging of steeps in current waveforms, identification o
 f \n   different chains turning-on patterns, etc. these all scenarios we h
 ave to take care.\n\n* Some cluster-based debug reports would be helpful h
 ere\n\n
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