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BEGIN:VEVENT
DTSTAMP:20260402T024534Z
LOCATION:Engineering Posters\, Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250623T170000
DTEND;TZID=America/Los_Angeles:20250623T180000
UID:dac_DAC 2025_sess263_ENGPOST344@linklings.com
SUMMARY:A Novel Approach For Logic Equivalence Check After Pipeline Retimi
 ng in ECO
DESCRIPTION:Naveen Bishnoi, Sardar Bhukya, Mohit Rawat, Sneha Biswas, and 
 Satish Sethuraman (Intel Corporation); Bassilios Petrakis (Cadence Design 
 Systems, Inc.); and Nilabh Srivastava (Intel Corporation)\n\nIn high-speed
  design we need to do manual eco to meet last miles timing paths. Pipeline
  Retiming is an optimization technique involves splitting and repositionin
 g of combinational logic across the sequential without changing its logica
 l functionality.\n\nCurrent EDA Logical Equivalence Check (LEC) Tools has 
 limitation to verify equivalence on sequential retiming because required i
 nformation does not get saved in json file.\n\nTo overcome the above limit
 ation of EDA vendor tool we are proposing a method to verify logical equiv
 alence check after pipeline retiming, which helped to improve the frequenc
 y limiting paths by 2% of cycle time\n\n
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