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DTSTAMP:20260402T024533Z
LOCATION:Engineering Posters\, Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250623T170000
DTEND;TZID=America/Los_Angeles:20250623T180000
UID:dac_DAC 2025_sess263_ENGPOST354@linklings.com
SUMMARY:A Safety Centric approach to Functional Verification of Dual Core 
 Lock-Step Designs
DESCRIPTION:Mohammad Rashid, Suharini C, Ratan Deep, and Harsh Setia (Sams
 ung Semiconductor)\n\nASIL requirements for automotive chips have resulted
  in implementation of functional safety features in several IPs. Dual Core
  Lock Step (DCLS) is one of the popular methods to achieve functional safe
 ty in medium to large IPs which require fine grain control. With many IPs 
 incorporating DCLS, the verification effort has increased exponentially ov
 er the years. This paper proposes a methodology to speed up the verificati
 on process by automating testbench generation and identifying potential is
 sues early in the design cycle. The generated testbench components viz che
 cker, error injector, scoreboard and driver, are SV/UVM compatible allowin
 g easy integration into existing legacy testbenches. The python based auto
 mation script also provides valuable insights into the lockstep design by 
 generating several reports for review with the designer and functional saf
 ety experts. A mathematical model is developed for evaluating the effectiv
 eness of DCLS in detecting drift between the primary and redundant cores. 
 The methodology is evaluated for numerous styles of DCLS implementations, 
 and enhancement knobs are introduced to reduce automation runtimes. The pr
 oposed methodology reduces the verification effort and time by several fol
 ds.\n\n
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