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DTSTAMP:20260402T024533Z
LOCATION:Engineering Posters\, Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250623T170000
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UID:dac_DAC 2025_sess263_ENGPOST361@linklings.com
SUMMARY:Congestion Free, Power Domain Aware Signal Multiplexing
DESCRIPTION:Dinesh Joshi and Nidhi Sinha (NXP Semiconductors)\n\nAutomotiv
 e SoCs with body control applications require a current profile supported 
 by the various power modes of the device. For body and gateway application
 s, power gating is a very commonly used technique to achieve the current p
 rofile. \nHence the MCU transitions to and from standby mode at regular in
 tervals. Driven from ultra-low power consumption requirement of the MCU in
  the standby mode, not all the IOs remain alive in standby mode, apart fro
 m the ones which would be used in the standby application. \n\nHence there
  is a need to configure the pad state of the device in standby mode based 
 on the low power application requirements. \n\nThe conventional signal mul
 tiplexing approaches suffer from congestion and routing issues since the I
 Os which have any always-on domain functionality reside in always on domai
 n, irrespective of other functions multiplexed on that IO.\n\nThe proposed
  signal multiplexing scheme resolves this by controlling the signal multip
 lexing in a modular fashion, thereby providing a congestion free, power do
 main aware signal multiplexing which reduces the buffering and congestion 
 in the signal routing. It also enables the software to govern the state of
  the pads in the standby mode and providing flexibility to achieve the low
 est current profile driven by the application by controlling functionality
  at per-pad basis.\n\n
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