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DTSTAMP:20260402T024534Z
LOCATION:Engineering Posters\, Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250624T170000
DTEND;TZID=America/Los_Angeles:20250624T180000
UID:dac_DAC 2025_sess264_ENGPOST071@linklings.com
SUMMARY:Guided Physical Power Optimization of AI Silicon
DESCRIPTION:Aditya Chandrasekar Ramachandran (Principal Engineer)\n\nIn th
 e realm of power optimization, focusing significant effort on power enhanc
 ement for key blocks is essential as blocks follow the Pareto Rule. Tradit
 ional unidirectional PD flows often fall short, potentially trapping desig
 ners in local minima. However, leveraging designers' insights on these key
  blocks can significantly improve power Quality of Results (QoR) if, at ev
 ery stage, PD designers analyze results to facilitate better trade-offs ea
 rlier in the flow. This presentation will discuss some approaches for guid
 ing initial phases of the flow based on analysis of opportunities availabl
 e in later stages of the flow and results thereof.\n\nTopics: Front-End De
 sign\n\n
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