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DTSTART:19700308T020000
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DTSTAMP:20260402T024534Z
LOCATION:Engineering Posters\, Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250624T170000
DTEND;TZID=America/Los_Angeles:20250624T180000
UID:dac_DAC 2025_sess264_ENGPOST095@linklings.com
SUMMARY:Innovative RDL PEX flow with Calibre, enhances design reliability 
 and performance
DESCRIPTION:Srilata Raman, Haritez Narisetty, and David Permana (GlobalFou
 ndries) and Yousry ElMaghraby and Salma Youssef (Siemens)\n\nExtracting th
 e Parasitic effect of packaging layers, such as redistribution layers (RDL
 ) is important to enhance the performance of the design, as seen to accoun
 t for more than 10% of the total parasitic capacitance on nets near RDL la
 yers: impacting the performance of the circuit. The Calibre nmPlatform int
 roduces an innovative RDL calibration and extraction flow (with xRC and xA
 CT) that enables both design houses and Foundries to optimize their PEX ev
 aluations, taking into account the RDL effect, while relying on the Foundr
 y-qualified decks for all base layers.\n        Designers can use the Cali
 bre xRC or Calibre xACT tools to perform PEX on layouts containing RDL lay
 ers using RDL Addon rule decks that provide highly consistent extraction r
 esults on base-layers and very high accuracy correlation on nets near RDL 
 layers. The new flow expedites the calibration and extraction process thro
 ugh a simple configuration of the RDL process file, relying entirely on th
 e qualified foundry decks in evaluating parasitics on the base layers' und
 erneath packaging.\n        In collab with GlobalFoundries, the results sh
 ow that the new robust RDL calibration and extraction approach is supporte
 d for most versions of Foundry-qualified decks. When the flow was tested o
 n layouts formerly exhibiting inaccuracies with conventional flows and the
  results were evaluated against qualified deck-based extraction, the resul
 ts showed high accuracy versus the reference solver solutions (within 3%) 
 with a more accurate insight of the final performance of the circuit after
  adding the RDL layers.\n\nTopics: Front-End Design\n\n
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