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DTSTAMP:20260402T024534Z
LOCATION:Engineering Posters\, Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250624T170000
DTEND;TZID=America/Los_Angeles:20250624T180000
UID:dac_DAC 2025_sess264_ENGPOST096@linklings.com
SUMMARY:Effective Ways of Analyzing and Optimizing Voltage Variation Chall
 enges for 3DIC Chips
DESCRIPTION:mingyang liu and Runjian Wang (Hangzhou Zhicun (Witmem) Techno
 logy Co., Ltd.); Ran Zhang (Ansys); Hengzhi Hu, minglu xu, and Yue Heng (H
 angzhou Zhicun (Witmem) Technology Co., Ltd.); Long Kong (Witmem); and Shu
 oyue Cui and Xiaomei You (Ansys)\n\nIn consumer products, there is a pursu
 it of low power consumption and small size. In the case of this article, t
 o enhance the computing power per unit area of the chip, multiple Storage 
 dies and a Logic die are stacked vertically. Each Die contains tens of tho
 usands of high-precision array units, storage array units, and digital uni
 ts. The requirements for voltage variation on the power supply and VSS are
  extremely strict.\nDue to the limitation of bump resources, the VSS of th
 e Storage and Logic Dies are combined on the Logic Die and then fan out to
  the VSS Bumps. It is necessary to simultaneously simulate the voltage var
 iation of the VSS TSV(Through Silicon Via) at each grounding point locatio
 n on the Storage Dies and the Logic DIE and then analyze and find an optim
 ization scheme for the voltage variation. \nIn this presentation, we provi
 des an effective analysis method for the Full Chip Voltage Variation of co
 mplex analog-digital hybrid Storage 3DIC, which can accurately analyze the
  voltage variation of VSS TSV at the grounding point locations.\nThen, two
  optimization methods are presented.\nThe first one is we optimizes the vo
 ltage variation of the power ground of the storage array by means of the c
 ontrolled delayed startup of array units. Using the method provided in thi
 s paper, the effectiveness of the scheme is demonstrated through the compa
 rison of simulation data.\nThe second one is through comparative analysis 
 of simulation data, we demonstrate that the mutual inductance between TSV 
 Cells cannot be ignored in multi-die stacking. Meanwhile, an  arrangement 
 scheme was provided that can reduces the mutual inductance between TSV cel
 ls effectively.\n\nTopics: Front-End Design\n\n
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