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DTSTAMP:20260402T024533Z
LOCATION:Engineering Posters\, Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250624T170000
DTEND;TZID=America/Los_Angeles:20250624T180000
UID:dac_DAC 2025_sess264_ENGPOST111@linklings.com
SUMMARY:Pattern-based Abstraction for Mixed Transistor-Level Static Timing
  Analysis
DESCRIPTION:Xin Zhao, Robert Allen, and Kerim Kalafala (IBM)\n\nTransistor
 -level static timing analysis plays a vital role in IBM high-performance p
 rocessors' design, allowing custom circuits to meet aggressive frequency a
 nd power goals. It enables designers to robustly determine timing critical
  paths based on simulation of transistor-level netlist incorporating logic
  and layout parasitic effects in advanced process nodes.\n\nPreviously, du
 e to analog nature or capacity concerns combined with extractor limitation
 s, designers had to abstract large portions of designs. "Grey boxing" coul
 d easily miss real layout problems or mis-estimate effects inside abstract
 s. \n\nThis talk will present a pattern-based abstraction timing methodolo
 gy for mixed transistor-level and abstract-based static timing analysis, w
 hich has been successfully leveraged by IBM in multiple microprocessor gen
 erations. This novel approach ensures truly layout-based timing analysis a
 nd rule generation by providing flexibility to precisely control timing ab
 straction on subsets of a netlist while modelling parasitic effects at tra
 nsistor level, achieving higher accuracy than prior methods. This methodol
 ogy has enhanced both design and EDA productivity with early enablement of
  circuits and easier support of complicated subcircuits; and it has reduce
 d analysis runtime by 3.7X to 9.6X, leading to faster timing signoff and e
 arlier delivery of rules to integrators.\n\nTopics: Front-End Design\n\n
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