BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20250625T183018Z
LOCATION:Engineering Posters\, Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250624T170000
DTEND;TZID=America/Los_Angeles:20250624T180000
UID:dac_DAC 2025_sess264_ENGPOST215@linklings.com
SUMMARY:Formal meets Simulation: Accelerate Verification closure using Mul
 tiplatform technologies
DESCRIPTION:Anunay Bajaj, Amrita Patil, and Kirti Srivastava (Cadence Desi
 gn Systems, Inc.)\n\nThis Paper leverages practical usage of UCIe/Chiplet 
 systems as a live testimony -  Formal verification and simulation/emulatio
 n verification of designs and proposes combining them for better results.\
 n\n        1.        Formal Verification:\n        •        Detects bugs e
 arly and allows reuse of tools across platforms.\n        •        However
 , it struggles with large designs and deep-state exploration, making it le
 ss effective for complex scenarios.\n\n        2.        Simulation/Emulat
 ion Verification:\n        •        Handles large designs and deep-state s
 imulations effectively.\n        •        However, debugging issues can ta
 ke days due to time-intensive failure analysis.\n\nHybrid Approach: Combin
 ing Both Methods\n\nRunning formal and simulation/emulation verification t
 ogether offers the best of both worlds:\n        •        Catch Early Bugs
 : Formal runs can quickly identify simple issues.\n        •        Faster
  Debugging: Assertions from formal runs can be reused in simulations, stop
 ping at failures to save time.\n        •        Consistency: Using shared
  properties across both platforms ensures consistent checks and constraint
 s.\n        •        Accelerated Coverage: Merging formal coverage with si
 mulation coverage helps achieve faster verification at the system-on-chip 
 (SoC) level.\n\nThis hybrid approach shows results of both methods - Speed
  up and improve the overall verification process, ensuring more reliable r
 esults and hence improving TAT\n\n
END:VEVENT
END:VCALENDAR