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BEGIN:VEVENT
DTSTAMP:20260402T024533Z
LOCATION:Engineering Posters\, Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250624T170000
DTEND;TZID=America/Los_Angeles:20250624T180000
UID:dac_DAC 2025_sess264_ENGPOST255@linklings.com
SUMMARY:Janus – twin-faced debugging -  Anecdotes from formal, security & 
 timing exception verification
DESCRIPTION:Srinivasan Venkataramanan (VerifWorks), Ajeetha Kumari Venkate
 san (AsFigo Technologies), and Hemamalini Sundaram (Verifworks)\n\nWe pres
 ent our experience with a custom flow named Janus, which enhances the debu
 gging process by converting formal verification traces into UVM tests, eff
 ectively bridging the gap between formal verification and dynamic simulati
 on. This dual approach improves bug detection and reduces debug efforts. B
 y leveraging formal verification (FV) to generate focused, concise trace d
 ata, Janus translates these traces into UVM-based simulation tests, enabli
 ng enhanced debugging and comprehensive coverage generation.\n\nThis techn
 ique is demonstrated in two key applications: security controller IP with 
 taint verification and LPDDR PHY controllers with timing exception handlin
 g. For the security controller, Janus uses formal verification to identify
  potential taint propagation vulnerabilities, which are then validated thr
 ough simulation to ensure secure data handling. For the LPDDR PHY controll
 er, timing exceptions—such as false path and multi-cycle path constraints 
 from the user's SDC file—are verified through formal methods, while the tr
 anslated UVM tests simulate realistic operational conditions to validate t
 he system.\n\nBy integrating formal verification with UVM simulation, Janu
 s significantly improves debugging efficiency (by a factor of 4 on an IP),
  while also providing detailed coverage generation. For the SDC verificati
 on, Janus successfully identified and verified 250+ failing exceptions in 
 simulation.\n\nTopics: Front-End Design\n\n
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