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DTSTAMP:20260402T024534Z
LOCATION:Engineering Posters\, Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250625T121500
DTEND;TZID=America/Los_Angeles:20250625T131500
UID:dac_DAC 2025_sess265_ENGPOST053@linklings.com
SUMMARY:Agentic AI Approach to Optimize Front-End EDA Tools Flow
DESCRIPTION:Nitin Pundir, Maya Safieddine, Arvind Haran, Rich Carbone, Fra
 nk Wallingford, Ali El-Zein, Viresh Paruthi, and Dan Coops (IBM)\n\nVerify
 ing server-grade Hardware Description Languages (HDLs) is a complex task t
 hat requires sophisticated front-end Electronic Design Automation (EDA) to
 ols. To optimize performance, these tools abstract the HDLs and utilize in
 termediate representations. During runtime, EDA tools may also append addi
 tional information to facilitate verification. However, this abstraction a
 nd annotation process can create a significant disconnect between the user
 's input and the tool's output, necessitating extensive manual interventio
 n from a subject matter expert to debug tool's error. \n\nArtificial Intel
 ligence (AI) can help bridge this gap and accelerate error interpretation 
 and debugging. Nevertheless, foundational AI models lack proprietary domai
 n/design-specific information. To address this limitation, AI agents can b
 e employed to leverage existing EDA tools and gather domain/design-specifi
 c information, thereby facilitating more accurate error interpretation and
  debugging. \n\nThis presentation will showcase the application of AI agen
 ts in IBM's static structural checking tool, which is intensively used to 
 ensure HDL compliance with IBM's design methodology. The tool operates on 
 abstracted HDLs represented as a graph of BOXES and NETS, utilizing ANTLR 
 grammar to traverse the graph. During traversal, the tool appends addition
 al labels and tags to facilitate checking. However, the resulting error tr
 aces are often cryptic and require expert interpretation, slowing down the
  debugging process. By integrating AI agents, we aim to bridge the gap bet
 ween tool errors and user understanding of the HDL, thereby accelerating d
 ebugging efforts by at least 30%. This innovative approach has the potenti
 al to significantly improve the efficiency and productivity of HDL verific
 ation and debugging processes.\n\n
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