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DTSTAMP:20260402T024533Z
LOCATION:Engineering Posters\, Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250625T121500
DTEND;TZID=America/Los_Angeles:20250625T131500
UID:dac_DAC 2025_sess265_ENGPOST133@linklings.com
SUMMARY:Novel Methodology to Address ESD Verification Complexity of 2.5D/3
 D-IC Designs
DESCRIPTION:Hirotaka Yamazaki (Socionext Inc.)\n\nAs the adoption of 2.5D/
 3D-ICs increases, it is essential to address new challenges that differ fr
 om those in conventional 2D-ICs. \nThere are two primary issues in 2.5D/3D
 -IC ESD verification: increased verification complexity and cost. It is ne
 cessary to check paths not only within a single die but also between dies,
  considering the integration of dies with different specifications, such a
 s technology nodes and ESD immunity levels (HBM/CDM). \nThe number of bump
 s is increasing and is expected to reach millions with hybrid bond technol
 ogy, leading to a dramatic increase in check paths, verification time, and
  debugging/feedback costs. \nTo address these challenges, we developed an 
 ESD verificationenvironment that reduces verification complexity in large-
 scale 2.5D-ICs and improves cost efficiency through two key processes. \nF
 or a large number of resistance checks between micro bumps, we programmati
 cally reduced verification time by extracting optimal check regions based 
 on cell placements and bump positions. Additionally, by mapping and visual
 izing the resistance check results between micro bumps, we clarified layou
 t weaknesses and facilitated easier layout fixes.\n\n
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