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DTSTAMP:20260402T024532Z
LOCATION:Engineering Posters\, Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250625T121500
DTEND;TZID=America/Los_Angeles:20250625T131500
UID:dac_DAC 2025_sess265_ENGPOST157@linklings.com
SUMMARY:A Solution for intermittently and Fastly Power On Repair
DESCRIPTION:Minqiang Peng (Sanechips Technology Co.,Ltd); Zhuo Wang (Synop
 sys); Feilong Pan, Tianjiao Wang, Junhua Qin, Hu Hai, Lei Chen, Keqing Ouy
 ang, and Guohua Zhou (Sanechips Technology Co.,Ltd); and Jian Yu and Fengf
 eng Tang (Synopsys)\n\nWith the continuous expansion of the chip scale and
  the pursuit of enhanced performance, augmenting the memory repair time du
 ring the power-up process has become increasingly arduous. This paper pres
 ents a novel structure that is designed to curtail the runtime of the memo
 ry hard repair process and bolster the efficiency of the full-chip repair 
 dispatcher, thereby facilitating high-speed full-chip repair.\nThis struct
 ure encompasses two principal components: the request scheduler and the In
 dex repair mechanism of the STAR memory system provided by Synopsys. In th
 e case jointly developed by Sanechips and Synopsys, within a repair clock 
 frequency of 100 MHz, the largest subsystem can repair any of three memori
 es within a mere 2.5 microseconds. Moreover, the full-chip repair, with ou
 t-of-order decoupling requests, can be accomplished within 5 microseconds.
 \n\n
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