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DTSTAMP:20260402T024534Z
LOCATION:Engineering Posters\, Level 2 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250625T121500
DTEND;TZID=America/Los_Angeles:20250625T131500
UID:dac_DAC 2025_sess265_ENGPOST367@linklings.com
SUMMARY:CDC-RDC Inter-operable collateral Standardization
DESCRIPTION:Anupam Bakshi (Agnisys Inc.), Bill Gascoyne (Blue Pearl Softwa
 re), and Don Mills (Microchip Technology Inc.)\n\nCDC-RDC analysis has evo
 lved as an inevitable stage in RTL quality signoff in the last two decades
 . Over this period, the designs have grown exponentially to SOC's having 2
  trillion+ transistors and chiplet's having 7+ SOC's. Today CDC verificati
 on has become a multifaceted effort across the chips designed for clients,
  servers, mobile, automotives, memory, AI/ML, FPGA etc… with focus on clea
 ning up of thousands of clocks and constraints, integrating the SVA's for 
 constraints in validation environment to check for correctness, looking fo
 r power domain and DFT logic induced crossings, finally signing off with n
 etlist CDC to unearth any glitches and corrupted synchronizers during synt
 hesis. \n\nAs the design sizes increased in every generation, the EDA tool
 s could not handle running flatly and the only way of handling design comp
 lexity was through hierarchical CDC-RDC analysis consuming abstracts. Also
 , hierarchical analysis helps to enable the analysis in parallel with team
 s across the globe. Even with all these significant progress in capabiliti
 es of EDA tools the major bottleneck in CDC-RDC analysis of complex SOC's 
 and Chiplets is consuming abstracts generated by different vendor tools. D
 ifferent vendor tool abstracts are seen because of multiple IP vendors, ev
 en in house teams might deliver abstracts generated with different vendors
  tools. \n\nThe Accellera CDC Working-Group aims to define a standard CDC-
 RDC IP-XACT / TCL model to be portable and reusable regardless of the invo
 lved verification tool.\n\nAs moving from monolithic designs to IP/SOC wit
 h IPs sourced from a small/select providers to sourcing IPs globally (to c
 reate differentiated products), the quality must be maintained as driving 
 faster time-to-market. In areas where the standards (SystemVerilog, OVM/UV
 M, LP/UPF) are present, the integration is able to meet the above (quality
 , speed). However, in areas where standards (in this case, CDC-RDC) are no
 t available, most options trade-off either quality, or time-to-market, or 
 both :-( Creating a standard for inter-operable collateral addresses this 
 gap.\n\n
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