BEGIN:VCALENDAR VERSION:2.0 PRODID:Linklings LLC BEGIN:VTIMEZONE TZID:America/Los_Angeles X-LIC-LOCATION:America/Los_Angeles BEGIN:DAYLIGHT TZOFFSETFROM:-0800 TZOFFSETTO:-0700 TZNAME:PDT DTSTART:19700308T020000 RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU END:DAYLIGHT BEGIN:STANDARD TZOFFSETFROM:-0700 TZOFFSETTO:-0800 TZNAME:PST DTSTART:19701101T020000 RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU END:STANDARD END:VTIMEZONE BEGIN:VEVENT DTSTAMP:20260402T024535Z LOCATION:Level 2 Lobby DTSTART;TZID=America/Los_Angeles:20250623T180000 DTEND;TZID=America/Los_Angeles:20250623T190000 UID:dac_DAC 2025_sess287@linklings.com SUMMARY:Late Breaking Results Posters DESCRIPTION:Late Breaking Results: Automated Topology Generation for Power Amplifier Designs through BiLSTM-based DNN and Multi-objective Optimizati ons\n\nThis work presents an automated methodology for optimizing power am plifier (PA) design by predicting the most suitable circuit topology. Bidi rectional long short-term memory (BiLSTM) deep neural network (DNN) is tra ined to determine the optimal PA topology, while multi-objective Pareto fr ont optimiz...\n\n\nLida Kouhalvandi (Dogus University); Sercan Aygun (Uni versity of Louisiana, Lafayette); M. Hassan Najafi (Case Western Reserve U niversity); and Arman Roohi (University of Illinois, Chicago)\n----------- ----------\nLate Breaking Results: BLAST: Bisection-Free Learning Approach for Statistical Timing Characterization\n\nStatistical timing characteriz ation for standard cells faces significant computational challenges due to the laborious bisection analysis for setup/hold constraint of sequential cells. To address this issue, we propose a Bisection-Free Learning Approac h for Statistical Timing Characterization (BLAST...\n\n\nKai Jing, Tao Bai , Zeyuan Deng, Junming Jiao, and Peng Cao (Southeast University)\n-------- -------------\nLate Breaking Results: Scalable GPU-Friendly Parallelizatio n for Sweep-Based Maze Routing\n\nGlobal routing is a critical stage in th e VLSI design flow, aiming to provide a robust guide for detailed routing and serve as early design feedback for placement. Many approaches have lev eraged GPU parallelization to achieve significant acceleration and reduce runtime. However, with the increasing ...\n\n\nCheng-Yu Chiang, Zong-Ying Cai, Chao-Chi Lan, Yan-Jen Chen, Yang Hsu, and Yao-Wen Chang (National Tai wan University) and Hung-Ming Chen (National Yang Ming Chiao Tung Universi ty)\n---------------------\nLate Breaking Results: Fine-Tuning LLMs for Te st Stimuli Generation\n\nThe understanding and reasoning capabilities of l arge language models (LLMs) with text data have made them widely used for test stimuli generation. Existing studies have primarily focused on method s such as prompt engineering or providing feedback to the LLMs' generated outputs to improve test stimu...\n\n\nHyeonwoo Park, Seonghyeon Park, and Seokhyeong Kang (Pohang University of Science and Technology (POSTECH))\n- --------------------\nLate Breaking Results: Breaking Symmetry--- Unconven tional Placement of Analog Circuits using Multi-Level Multi-Agent Reinforc ement Learning\n\nLayout-dependent effects (LDEs) significantly impact ana log circuit performance. Traditionally, designers have relied on symmetric placement of circuit components to mitigate variations caused by LDEs. Ho wever, due to non-linear nature of these effects, conventional methods oft en fall short. We prop...\n\n\nSupriyo Maji, Linran Zhao, Souradip Poddar, and David Pan (The University of Texas at Austin)\n---------------------\ nLate Breaking Results: Hybrid Logic Optimization with Predictive Self-Sup ervision\n\nHybrid optimization is an emerging approach in logic synthesis , focusing on applying diverse optimization methods to different parts of a logic circuit. This paper analyzes the relationship between each vertex and its corresponding optimization method. We extract a subgraph centered on each vertex a...\n\n\nRongliang Fu (The Chinese University of Hong Kong ); Ran Zhang (Institute of Computing Technology, Chinese Academy of Scienc es); Ziyang Zheng, Zhengyuan Shi, and Yuan Pu (The Chinese University of H ong Kong); Junying Huang (Institute of Computing Technology, Chinese Acade my of Sciences); and Qiang Xu and Tsung-Yi Ho (The Chinese University of H ong Kong)\n---------------------\nLate Breaking Results: Decentralized Vot ing-Based Attestation for IoT Devices\n\nRemote Attestation (RA) has becom e a valuable security service for Internet of Things (IoT) devices, as the security of these devices is often not prioritized during the manufacturi ng process. However, traditional RA schemes suffer from a single point of failure because they rely on a trusted verifi...\n\n\nMohamed Alsharkawy, Eren Sönmez, Jeferson Gonzalez-Gomez, Hassan Nassar, and Joerg Henkel (Kar lsruhe Institute of Technology)\n---------------------\nLate Breaking Resu lts: Versatile 4:1 Multiplexer Using 1T1R RRAM Crossbar for High Speed In- Memory Computing\n\nThis paper presents a high speed NAND based 4:1 Multip lexer (MUX) for various logic operations in a Resistive-Random access memo ry crossbar structure. Compared to existing 4:1 MUX designs that require 1 0 steps, our proposed method completes execution in 3 steps. Additionally, proposed 4:1 MUX\nbased ...\n\n\nVinod Kumar and Binsu Kailath (Indian In stitute of Information Technology Design and Manufacturing Kancheepuram)\n ---------------------\nLate Breaking Results: FPGen-3D: Automated Framewor k for 3D-FPGA Architecture Generation and Exploration\n\nIn this work, we propose FPGen-3D, an automated framework for 3D field-programmable gate ar rays (FPGA) architecture generation and exploration. FPGen-3D generates cu stom 3D FPGA fabrics based on user-defined architectural parameters, produ cing synthesizable register-transfer level (RTL) code, routin...\n\n\nIsma el Youssef and Cong "Callie" Hao (Georgia Institute of Technology)\n------ ---------------\nLate Breaking Results: Utilization of Hybrid Threshold-Vo ltage Flip-flops for Power Recovery\n\nAs the process technology advances, reducing the leakage power as much as possible is one of the utmost chall enging tasks in chip implementation. Utilizing cells with multi-VT (thresh old voltage) is known to be a very effective method for optimizing leakage power under timing constraints. However, f...\n\n\nSehyeon Chung (Seoul N ational University); Hyunchul Hwang, Byungsu Kim, Jaeha Lee, and Kunhyuk K ang (Samsung); and Taewhan Kim (Seoul National University)\n-------------- -------\nLate Breaking Results: Warpage-Aware Generative Floorplanning for Reliable Advanced Packaging\n\nThis paper presents the first warpage-awar e generative learning-based floorplanning algorithm to effectively model t he warpage effect and optimize the die floorplan on a fixed outlined subst rate. With more heterogeneous materials and dense interconnects in advance d packaging, warpage is a main relia...\n\n\nMin-Hung Chen, Cheng-Yen Li, Chuan-Chi Su, and Yao-Wen Chang (National Taiwan University) and Tung-Chie h Chen (Synopsys)\n---------------------\nLate Breaking Results: Statistic al Timing Graph Scheduling Algorithm for GPU Computation\n\nStatistical St atic Timing Analysis (SSTA) is a crucial technique in digital circuit desi gn because it addresses on-chip variations (OCV) by propagating timing dis tributions instead of fixed delays. However, the computational complexity of SSTA demands significant memory and long runtimes. While GPUs...\n\n\nC hih-Chun Chang and Tsung-Wei Huang (University of Wisconsin, Madison)\n--- ------------------\nLate Breaking Results: Less Sense Makes More Sense: In -Sensor Compressive Learning for Efficient Machine Vision\n\nIntegrating d eep learning and image sensors has significantly transformed machine visio n applications. Yet, conventional high-resolution image acquisition scheme s enabled by imagers are energy-inefficient for deep learning, as they inv olve excessive data quantization and transmission overhead. To ad...\n\n\n Yiwen Liang and Weidong Cao (George Washington University)\n-------------- -------\nLate Breaking Results: On-the-Fly Hadamard Hypervector Processing for Efficient Hyperdimensional Computing\n\nInspired by the human brain, Hyperdimensional Computing (HDC) processes information efficiently by oper ating in high-dimensional space using hypervectors. While previous works f ocus on optimizing pregenerated hypervectors in software, this study intro duces a novel on-the-fly vector generation method...\n\n\nAbu Kaiser Moham mad Masum (University of Louisiana, Lafayette); Shoushtari Moghadam (Case Western Reserve University); Sabrina Hassan Moon and Ahmed Mamdouh (Univer sity of South Florida); M. Hassan Najafi (Case Western Reserve University) ; Dayane Reis (University of South Florida); and Sercan Aygun (University of Louisiana, Lafayette)\n---------------------\nLate Breaking Results: A Geometric Diffusion Model for Macro Placement Generation\n\nMacro placemen t is crucial in VLSI design, directly impacting circuit performance. We in troduce MacroDiff, a diffusion-based macro placement generative model that captures wirelength relationships instead of directly predicting macro co ordinates. By leveraging wirelength as an intermediate represent...\n\n\nJ ongho Yoon (Pohang University of Science and Technology (POSTECH)); Jinsun g Jeon (University of California, San Diego); and Seokhyeong Kang (Pohang University of Science and Technology (POSTECH))\n---------------------\nLa te Breaking Results: Encoder-Decoder Generative Diffusion Transformer Towa rds Push-Button Analog IC Sizing\n\nIn this paper, disruptive research usi ng generative diffusion models (DMs) with an attention-based encoder-decod er backbone is conducted to automate the sizing of analog integrated circu its (ICs). Unlike time-consuming optimization-based methods, the encoder-d ecoder DM is able to sample accurate sol...\n\n\nFilipe Azevedo, Nuno Lour enco, and Ricardo Martins (Universidade de Lisboa)\n---------------------\ nLate Breaking Results: Opera: An Open and Efficient Platform for Data-dri ven Synthesis of Analog Circuits\n\nThe front-end synthesis of analog circ uits has been a long-standing challenge since the advent of integrated cir cuits. Many methods, ranging from conventional optimization-based techniqu es to emerging learning-based approaches, have been extensively explored t o address this challenge. Yet, these met...\n\n\nShikai Wang (George Washi ngton University), Yaolong Hu (Rice University), Zhiqiang Yi (George Washi ngton University), Taiyun Chi (Rice University), and Weidong Cao (George W ashington University)\n---------------------\nLate Breaking Results: In-Me mory Arithmetic: Enabling Division with Stochastic Logic\n\nDesigning an e fficient arithmetic division circuit has long been a significant challenge . Traditional binary computation methods rely on complex algorithms that r equire multiple cycles, complex control logic, and substantial hardware re sources. Implementing division with emerg- ing in-memory computi...\n\n\nF arzad Razi (University of Minnesota); Mehran Shoushtari Moghadam and M. Ha ssan Najafi (Case Western Reserve University); Sercan Aygun (University of Louisiana, Lafayette); and Marc Riedel (University of Minnesota)\n------- --------------\nLate Breaking Results: A Diffusion-Based Framework for Con figurable and Realistic Multi-Storage Trace Generation\n\nWe propose DiTTO , a novel diffusion-based frame- work for generating realistic, precisely configurable, and diverse multi-device storage traces. Leveraging advanced diffusion techniques, DiTTO enables the synthesis of high-fidelity contin uous traces that capture temporal dynamics and inter-device de...\n\n\nSeo hyun Kim, Junyoung Lee, and Jongho Park (Daegu Gyeongbuk Institute of Scie nce and Technology); Jinhyung Koo and Sungjin Lee (Pohang University of Sc ience and Technology (POSTECH)); and Yeseong Kim (Daegu Gyeongbuk Institut e of Science and Technology)\n---------------------\nLate Breaking Results : Multi-Objective Multi-Bit Flip-Flop Placement Considering Pre-Placed Cel ls\n\nClustering single-bit flip-flops (SBFFs) into multi-bit flip-flops ( MBFFs) effectively reduces power and area. However, excessive displacement during the clustering and legalization process may incur significant timi ng degradation. To address this issue, we propose the first comprehensive MBFF place...\n\n\nCheng-Yen Li, Chuan-Chi Su, Zheng-Wei Chen, Shao-Hsiang Chen, and Yao-Wen Chang (National Taiwan University)\n------------------- --\nLate Breaking Results: Advanced PCB Placement with Irregular Component s for Efficient Collision Detection and Routability Optimization\n\nThis p aper introduces an automated placement framework to optimize component pos itioning on modern printed circuit boards (PCBs), addressing challenges po sed by heterogeneous components, irregular geometries, and complex design rules. The framework employs three key techniques to enhance placement q.. .\n\n\nChien-Hao Tsou, Zhu-Xun Lee, and Yao-Wen Chang (National Taiwan Uni versity)\n---------------------\nLate Breaking Results: Source-Aware Adapt ive Cache Management for CXL-enabled Disaggregated Memory Sharing\n\nDynam ic workloads running on multiple hosts will bring changing access patterns on CXL-enabled shared disaggregated memory. Existing works often un-trace ably cache multi-source accesses, making it hard to exploit each host's ac cess behavior and assure service quality. Our solution Alchemy jointly op. ..\n\n\nQianyu Cheng, JiaJun Ji, Teng Wang, Zihan Wang, Lei Gong, Chao Wan g, and Xuehai Zhou (University of Science and Technology of China)\n------ ---------------\nLate Breaking Results: Novel Design of MTJ-Based Unified LIF Spiking Neuron and PUF\n\nDue to the higher energy and hardware effici ency of spiking neural networks (SNNs) compared to deep neural networks, t hey have attracted a lot of attention. However, their security must be inv estigated, given that they have access to private and confidential data. P hysically unclonable functions (PU...\n\n\nMilad Tanavardi Nasab, Wu Yang, and Himanshu Thapliyal (University of Tennessee, Knoxville)\n------------ ---------\nLate Breaking Results: A Fast Nearest Neighbor Search Accelerat ion for 3D Point Cloud\n\nThis paper presents FastNN, a novel accelerator architecture for efficient K-Nearest Neighbors (KNN) search in point cloud s. FastNN leverages a locality-sensitive E2LSH partitioning method and a p re-comparator module to significantly reduce the candidate search space an d minimize the number of Eucli...\n\n\nJinao Li, Teng Wang, Qianyu Cheng, Zhendong Zheng, Lei Gong, Chao Wang, Xi Li, and Xuehai Zhou (University of Science and Technology of China)\n---------------------\nLate Breaking Re sults: Customized Diffusion Model Empowered by Heterogeneous Graph Network for Effective Floorplanning\n\nIn this paper, we propose a customized dif fusion model to directly generate high-quality initial floorplans. \nBy le veraging a classical analytical-based floorplanner on top of this initial floorplan, the final floorplanning results are significantly improved.\nTo enhance feature extraction, a heterog...\n\n\nXinglin Zheng, Hao Gu, Keyu Peng, and Youwen Wang (Southeast University); Wenxing Zhu (Fuzhou Univers ity); and Ziran Zhu (Southeast University)\n---------------------\nLate Br eaking Results: An Efficient and Scalable Track Assignment with GPU Parall elism\n\nThe track assignment has been introduced between the global routi ng and the detailed routing. Based on the independence and divisibility of track assignment, we propose a GPU-accelerated parallel track assignment algorithm. To estimate the routability more accurately, the algorithm prop oses a track ...\n\n\nGenggeng Liu, Pengcheng Huang, and Zepeng Li (Fuzhou University); Wen-Hao Liu (Nvidia); Xing Huang (Northwestern Polytechnical University); and Wenzhong Guo (Fuzhou University)\n---------------------\ nLate Breaking Results: The Hidden Risks of Activation Duration in PLPUFs\ n\nThe security of Internet of Things (IoT) devices is crucial to protect the vast amounts of data exposed due to their widespread adoption. Authent ication is one of the key aspects of IoT security, but it becomes increasi ngly challenging, especially for resource-constrained devices that require lightw...\n\n\nMohamen Alsharkawy, Jan Zwerschke, Hassan Nassar, Jeferson Gonzalez-Gomez, and Joerg Henkel (Karlsruhe Institute of Technology) END:VEVENT END:VCALENDAR