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DTSTART:19700308T020000
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DTSTAMP:20260402T024533Z
LOCATION:Level 2 Lobby
DTSTART;TZID=America/Los_Angeles:20250623T180000
DTEND;TZID=America/Los_Angeles:20250623T190000
UID:dac_DAC 2025_sess287_LBR102@linklings.com
SUMMARY:Late Breaking Results: Statistical Timing Graph Scheduling Algorit
 hm for GPU Computation
DESCRIPTION:Chih-Chun Chang and Tsung-Wei Huang (University of Wisconsin, 
 Madison)\n\nStatistical Static Timing Analysis (SSTA) is a crucial techniq
 ue in digital circuit design because it addresses on-chip variations (OCV)
  by propagating timing distributions instead of fixed delays. However, the
  computational complexity of SSTA demands significant memory and long runt
 imes. While GPUs offer opportunities to accelerate SSTA, their limited mem
 ory caapacity makes it challenging to handle large-scale SSTA workloads. T
 o address this challenge, we propose a statistical timing graph (STG) sche
 duling algorithm combined with a GPU memory management strategy. We have s
 hown up to 4.9x speedup on a GPU with 16 GB memory compared to a 20-thread
  CPU baseline when solving an 18.2 GB STG.\n\n
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