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DTSTART;TZID=America/Los_Angeles:20250623T180000
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UID:dac_DAC 2025_sess287_LBR109@linklings.com
SUMMARY:Late Breaking Results: Utilization of Hybrid Threshold-Voltage Fli
 p-flops for Power Recovery
DESCRIPTION:Sehyeon Chung (Seoul National University); Hyunchul Hwang, Byu
 ngsu Kim, Jaeha Lee, and Kunhyuk Kang (Samsung); and Taewhan Kim (Seoul Na
 tional University)\n\nAs the process technology advances, reducing the lea
 kage power as much as possible is one of the utmost challenging tasks in c
 hip implementation. Utilizing cells with multi-VT (threshold voltage) is k
 nown to be a very effective method for optimizing leakage power under timi
 ng constraints. However, for the sequential cells on the timing critical p
 aths in circuits, there is no easy way for the multi-VT method to reduce t
 he leakage power unless timing is not sacrificed. To overcome this barrier
 , we introduce a set of new standard cells called hybrid-VT flip-flop cell
 s, each of which is implemented with two different VT types, one implanted
  onto its master latch while the other onto its slave latch, by which the 
 setup time and clock-to-Q delay can be controlled individually and indepen
 dently. We confirm that applying our power recovery method utilizing hybri
 d-VT flip-flop cells to the benchmark circuits, which have already been op
 timized by the conventional multi-VT cells, is able to further reduce the 
 leakage power by 8.97% with no timing degradation.\n\n
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