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LOCATION:Level 2 Lobby
DTSTART;TZID=America/Los_Angeles:20250623T180000
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UID:dac_DAC 2025_sess287_LBR112@linklings.com
SUMMARY:Late Breaking Results: In-Memory Arithmetic: Enabling Division wit
 h Stochastic Logic
DESCRIPTION:Farzad Razi (University of Minnesota); Mehran Shoushtari Mogha
 dam and M. Hassan Najafi (Case Western Reserve University); Sercan Aygun (
 University of Louisiana, Lafayette); and Marc Riedel (University of Minnes
 ota)\n\nDesigning an efficient arithmetic division circuit has long been a
  significant challenge. Traditional binary computation methods rely on com
 plex algorithms that require multiple cycles, complex control logic, and s
 ubstantial hardware resources. Implementing division with emerg- ing in-me
 mory computing technologies is even more challenging due to susceptibility
  to noise, process variation, and the complexity of binary division. In th
 is work, we propose an in-memory division architecture leveraging stochast
 ic computing (SC), an emerging technology known for its high fault toleran
 ce and low-cost design. Our approach utilizes a magnetic tunnel junction (
 MTJ)-based memory architecture to efficiently execute logic-in-memory oper
 ations. Experimental results across various process variation conditions d
 emonstrate the robustness of our method against hardware variations. To as
 sess its practical effectiveness, we apply our approach to the Retinex Alg
 orithm for image enhancement, demonstrating its viability in real-world ap
 plications.\n\n
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