BEGIN:VCALENDAR
VERSION:2.0
PRODID:Linklings LLC
BEGIN:VTIMEZONE
TZID:America/Los_Angeles
X-LIC-LOCATION:America/Los_Angeles
BEGIN:DAYLIGHT
TZOFFSETFROM:-0800
TZOFFSETTO:-0700
TZNAME:PDT
DTSTART:19700308T020000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=2SU
END:DAYLIGHT
BEGIN:STANDARD
TZOFFSETFROM:-0700
TZOFFSETTO:-0800
TZNAME:PST
DTSTART:19701101T020000
RRULE:FREQ=YEARLY;BYMONTH=11;BYDAY=1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTAMP:20260402T024534Z
LOCATION:Level 2 Lobby
DTSTART;TZID=America/Los_Angeles:20250623T180000
DTEND;TZID=America/Los_Angeles:20250623T190000
UID:dac_DAC 2025_sess287_LBR122@linklings.com
SUMMARY:Late Breaking Results: Multi-Objective Multi-Bit Flip-Flop Placeme
 nt Considering Pre-Placed Cells
DESCRIPTION:Cheng-Yen Li, Chuan-Chi Su, Zheng-Wei Chen, Shao-Hsiang Chen, 
 and Yao-Wen Chang (National Taiwan University)\n\nClustering single-bit fl
 ip-flops (SBFFs) into multi-bit flip-flops (MBFFs) effectively reduces pow
 er and area. However, excessive displacement during the clustering and leg
 alization process may incur significant timing degradation. To address thi
 s issue, we propose the first comprehensive MBFF placement methodology tha
 t addresses excessive displacement caused by pre-placed cells during clust
 ering and legalization while simultaneously optimizing timing, power, area
 , and bin utilization. Our methodology includes three main features: (1) a
  force model to relocate flip-flops and reduce timing violations, (2) a cl
 ustering and legalization process to reduce timing degradation caused by d
 isplacement, and (3) a multi-objective function to identify flip-flop cand
 idates suitable for MBFF clustering. Our methodology outperforms all parti
 cipating teams in the 2024 CAD Contest at ICCAD on Power and Timing Optimi
 zation Using Multi-Bit Flip-Flops, based on exactly the same settings\n\n
END:VEVENT
END:VCALENDAR
