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BEGIN:VEVENT
DTSTAMP:20260402T024534Z
LOCATION:Level 2 Lobby
DTSTART;TZID=America/Los_Angeles:20250623T180000
DTEND;TZID=America/Los_Angeles:20250623T190000
UID:dac_DAC 2025_sess287_LBR123@linklings.com
SUMMARY:Late Breaking Results: Opera: An Open and Efficient Platform for D
 ata-driven Synthesis of Analog Circuits
DESCRIPTION:Shikai Wang (George Washington University), Yaolong Hu (Rice U
 niversity), Zhiqiang Yi (George Washington University), Taiyun Chi (Rice U
 niversity), and Weidong Cao (George Washington University)\n\nThe front-en
 d synthesis of analog circuits has been a long-standing challenge since th
 e advent of integrated circuits. Many methods, ranging from conventional o
 ptimization-based techniques to emerging learning-based approaches, have b
 een extensively explored to address this challenge. Yet, these methods are
  data-driven and often suffer from low design efficiency, due to their hea
 vy reliance on time-consuming circuit simulators, which are frequently use
 d in the synthesis loop for real-time evaluation of the evolving circuit d
 esign. In addition, benchmarking these methods is also largely unachievabl
 e due to their exclusive use of commercial semiconductor technology for ev
 aluation. This "Late Breaking Results" introduces Opera, an open and effic
 ient platform for the data-driven synthesis of analog circuits. Specifical
 ly, Opera develops efficient surrogate models for various circuits and int
 egrates them into open-source OpenAI Gym-like environments to enable effic
 ient synthesis. Case studies on exemplary circuits show that this platform
  can accelerate the conventional data-driven synthesis flow by up to 40×. 
 It also enables the benchmarking of various synthesis methods with standar
 dized environments built upon an open-source semiconductor process.\n\n
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