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LOCATION:Level 2 Lobby
DTSTART;TZID=America/Los_Angeles:20250623T180000
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UID:dac_DAC 2025_sess287_LBR127@linklings.com
SUMMARY:Late Breaking Results: Scalable GPU-Friendly Parallelization for S
 weep-Based Maze Routing
DESCRIPTION:Cheng-Yu Chiang, Zong-Ying Cai, Chao-Chi Lan, Yan-Jen Chen, Ya
 ng Hsu, and Yao-Wen Chang (National Taiwan University) and Hung-Ming Chen 
 (National Yang Ming Chiao Tung University)\n\nGlobal routing is a critical
  stage in the VLSI design flow, aiming to provide a robust guide for detai
 led routing and serve as early design feedback for placement. Many approac
 hes have leveraged GPU parallelization to achieve significant acceleration
  and reduce runtime. However, with the increasing size and complexity of m
 odern large-scale designs, recent GPU-accelerated maze routing approaches,
  driven by the sweep operation, struggle to find solutions efficiently wit
 hin limited GPU memory resources. In order to address this issue, this pap
 er proposes a scalable, GPU-friendly sweep-based maze routing methodology 
 that requires significantly less memory and kernel function calls while ac
 celerating overall runtime. We introduce a sweep-sharing technique that al
 lows multiple nets to be routed simultaneously within a single sweeping pr
 ocess, significantly enhancing memory efficiency and reducing kernel launc
 hing overhead. We further propose an edge-level rip-up-and-reroute techniq
 ue that selectively reroutes only overflowed segments, preserving feasible
  parts of the solution and substantially reducing runtime. Experimental re
 sults on the latest ISPD'24 Contest benchmarks demonstrate that our GPU-fr
 iendly maze routing with sweep-sharing technique can significantly improve
  the efficiency over the state-of-the-art GPU-accelerated maze router.\n\n
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