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DTSTAMP:20260402T024533Z
LOCATION:Exhibitor Forum\, Level 1 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250625T120000
DTEND;TZID=America/Los_Angeles:20250625T123000
UID:dac_DAC 2025_sess303_EF121@linklings.com
SUMMARY:Engineering the Semiconductor Digital Thread
DESCRIPTION:Vishal Moondhra (Perforce Software) and Michael Munsey (Siemen
 s)\n\nThe rise of software-defined systems has fundamentally reshaped the 
 product development landscape. In this new paradigm, software architecture
  no longer follows hardware—it leads it. \n\nAs functionality and innovati
 on become increasingly defined by code, semiconductor and systems developm
 ent organizations must navigate unprecedented complexity: from the exponen
 tial growth of cross-domain data to the unique challenges of 3D IC and chi
 plet-based architectures, as well as the need for requirements traceabilit
 y and collaboration across mechanical, electrical, and software domains. I
 nsights must also be synthesized from disparate sources—a challenge compou
 nded by the complex task of maintaining data links across various levels o
 f IC and system integration. \n\nThis presentation explores the concept of
  the Semiconductor Digital Thread—a holistic, integrated approach to manag
 ing the complete semiconductor lifecycle in the era of software-defined de
 sign. Built on a seamless and fully traceable flow of data throughout the 
 product development lifecycle and a unified environment for hardware/softw
 are co-design, the Semiconductor Digital Thread can unlock new levels of p
 roductivity, innovation, and quality. \n\nBy integrating IP lifecycle mana
 gement and data management with EDA, PLM, and DevOps toolchains, semicondu
 ctor organizations can enable a data-driven digital thread that spans from
  initial system-level architecture through physical design and verificatio
 n. This digital thread provides the foundation for AI-powered, real-time a
 nalytics, helping engineers and business leaders alike to make informed de
 sign decisions that reduce risk and accelerate time to market.\n\nWhether 
 your focus is optimizing silicon cost, meeting aggressive power/performanc
 e targets, ensuring compliance, or boosting efficiency through effective I
 P reuse, the Semiconductor Digital Thread offers a blueprint for competiti
 ve advantage in the era of software-defined, AI-powered, silicon-enabled p
 roduct innovation.\n\n
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