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DTSTAMP:20260402T024534Z
LOCATION:Exhibitor Forum\, Level 1 Exhibit Hall
DTSTART;TZID=America/Los_Angeles:20250623T170000
DTEND;TZID=America/Los_Angeles:20250623T173000
UID:dac_DAC 2025_sess311_EF118@linklings.com
SUMMARY:Powering AI infrastructure with innovations in reliable in system/
 on-die memory design and characterization
DESCRIPTION:Ehsan Rashid, Chetan Kumar, Shreekanth Sampigethaya, and Kames
 h Akundi (Infosys)\n\nDriven by the frantic pace of Large Language Model a
 doption, AI is dramatically redefining Data Center Infrastructure requirem
 ents. For instance, Meta's Llama 3 needed 16,000 Nvidia Hopper GPUs and 70
  days to train, negotiating 405 Billion parameters and using 15.6 Trillion
  tokens. Such massive workloads demand not only optimally fast interconnec
 ts and innovations in Power delivery, but they also demand materially supe
 rior design and reliability performance from Compute's eternal execution t
 win - Memory, both on and off chip. Memory requirements for High Performan
 ce compute are an increasing challenge as new versions of LLMs (eg. Llama 
 3.1) are pushing per-model-instance memory requirements to nearly a Teraby
 te (854 GB to be precise), which in turn means subsequent generations of G
 PUs (like the H200) and other general purpose SoCs will have to support si
 gnificantly larger on-die Memory clusters. Designing, characterizing and d
 elivering reliable Memory banks within acceptable time-to-market windows t
 hus becomes a key competency that deserves increasing focus. Our design te
 am's track record of delivering multiple generations of silicon proven Mem
 ory IP in the most advanced process nodes across multiple foundries and cu
 stomers, enables us to be a significant part of that focus. Our design exp
 erience is enhanced by addressing advanced testability demands of modern m
 ulti-die SOCs, including proven history of designing on-chip memory diagno
 stics (to enable real-time fault monitoring without need for external test
 ers), supporting pattern diagnosis, debug, flexible repair hierarchies and
  Quality of results optimization, all techniques for non-intrusive fault t
 olerance and optimal system performance essential for AI/ML applications.\
 nDouble-click on our expertise and you will find Infosys employing robust 
 AI/ML powered algorithms in the Memory design and characterization process
 . Using these algorithms, we are identifying critical paths within large m
 emory instances, predicting PPA metrics across different process, voltage 
 and temperature corners and aging corners efficiently. These techniques dr
 amatically reduce memory design times by eliminating the need to run actua
 l simulations across all corners. Any design/feature change requires re-ch
 aracterization and model retraining ONLY over the corresponding leaf cell(
 s) while complier range change does not require any further adjustments. S
 uch innovations, using AI to power development of future AI platforms, is 
 one of many reasons why Infosys is a dependable partner in delivering core
  (Silicon) elements of AI infrastructure.\n\n
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